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Espressif Systems /ESP32-S2 /EXTMEM /CACHE_SYNC_INT_CTRL

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Interpret as CACHE_SYNC_INT_CTRL

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (PRO_ICACHE_SYNC_INT_ST)PRO_ICACHE_SYNC_INT_ST 0 (PRO_ICACHE_SYNC_INT_ENA)PRO_ICACHE_SYNC_INT_ENA 0 (PRO_ICACHE_SYNC_INT_CLR)PRO_ICACHE_SYNC_INT_CLR 0 (PRO_DCACHE_SYNC_INT_ST)PRO_DCACHE_SYNC_INT_ST 0 (PRO_DCACHE_SYNC_INT_ENA)PRO_DCACHE_SYNC_INT_ENA 0 (PRO_DCACHE_SYNC_INT_CLR)PRO_DCACHE_SYNC_INT_CLR

Description

register description

Fields

PRO_ICACHE_SYNC_INT_ST

The bit is used to indicate the interrupt by icache sync done.
PRO_ICACHE_SYNC_INT_ENA

The bit is used to enable the interrupt by icache sync done.
PRO_ICACHE_SYNC_INT_CLR

The bit is used to clear the interrupt by icache sync done.
PRO_DCACHE_SYNC_INT_ST

The bit is used to indicate the interrupt by dcache sync done.
PRO_DCACHE_SYNC_INT_ENA

The bit is used to enable the interrupt by dcache sync done.
PRO_DCACHE_SYNC_INT_CLR

The bit is used to clear the interrupt by dcache sync done.

Links

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Register License

Copyright 2024 Espressif Systems (Shanghai) PTE LTD

Licensed under the Apache License, Version 2.0 (the “License”); you may not use this file except in compliance with the License. You may obtain a copy of the License at

http://www.apache.org/licenses/LICENSE-2.0

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data